1. Field of the Invention
The present invention pertains to a method of fabricating openings, and more particularly, to a method of forming openings such as contact holes, via holes, and trenches, capable of preventing polymer residues and contact-to-contact bridge.
2. Description of the Prior Art
The trend to micro-miniaturization, or the ability to fabricate semiconductor devices with feature size smaller than 0.065 micrometers, has presented difficulties when attempting to form contact holes (especially for high aspect ratio contact holes) in a dielectric layer to expose underlying conductive regions.
Please refer to FIGS. 1-4. FIGS. 1-4 are schematic, cross-sectional diagrams showing the process of forming contact holes in accordance with the prior art method. As shown in FIG. 1, a metal-oxide-semiconductor (MOS) transistor device 20 is formed on a semiconductor substrate 10. The MOS transistor device 20, which is isolated by shallow trench isolations (STIs) 24, includes source/drain regions 12, a gate electrode 14, and a spacer structure 16 disposed on the sidewalls of the gate electrode 14. The semiconductor substrate 10 further includes a contact etch stop layer (CESL) 32 deposited over the MOS transistor device 20 and the semiconductor substrate 10, and an inter-layer dielectric (ILD) layer 34 deposited on the CESL 32. Subsequently, a bottom anti-reflective coating (BARC) layer 36 is deposited on the ILD layer 34. Then, a photoresist layer 40 is formed on the BARC layer 36, and a conventional exposure-and-development process is carried out to form openings 42 in the photoresist layer 40 to define the locations of contact holes to be formed later.
As shown in FIG. 2, using the photoresist layer 40 as an etching hard mask to etch the exposed BARC layer 36 and the ILD layer 34 through the openings 42 so as to form openings 44. The etching of the ILD layer 34 stops on the CESL 32. Subsequently, as shown in FIG. 3, using the remaining photoresist layer 40 and the BARC layer 36 as an etching hard mask to etch the exposed CESL 32 through the openings 44, thereby forming contact holes 46. As shown in FIG. 4, the remaining photoresist layer 40 and the BARC layer 36 over the ILD layer 34 are removed.
The above-described prior art method of forming contact holes has several drawbacks. First, when etching the CESL 32, the contact profile is also impaired due to the low etching selectivity between the ILD layer 34 and the CESL 32. Second, the ILD layer 34 and the underlying CESL 32 are etched in-situ, without removing the photoresist layer 40. The polymer residue produced during the etching of the ILD layer 34 and the CESL 32 results in a tapered profile of the contact hole 46, thereby reducing the exposed surface area of the source/drain regions 12 and increasing the contact sheet resistance.
In addition to the above problems, when the feature size is reduced to 0.045 micrometers or less, the CESL 32 disposed in between two adjacent gate electrodes 14 tends to merge, and causes seam issue. Under such a condition, the plug metal e.g. tungsten, which is filled into the contact hole 44 successively will fill into the seam and lead to contact to contact bridge. Please refer to FIGS. 5-8. FIGS. 5-8 are schematic diagrams illustrating the seam issue and contact-to-contact bridge according to conventional method. FIGS. 5-8 are cross-sectional views, where FIG. 8 is a perpendicular cross-sectional view of FIG. 7. As shown in FIG. 5, a plurality of MOS transistor devices 20 are formed on a semiconductor substrate 10 in a SRAM region for instance. The MOS transistor devices 20 include source/drain regions 12 disposed in the semiconductor substrate 10 between two adjacent gate electrodes 14, and a spacer structure 16 disposed on the sidewalls of the gate electrode 14. The semiconductor substrate 10 further includes a CESL 32 deposited over the MOS transistor devices 20 and the semiconductor substrate 10, and an ILD layer 34 deposited on the CESL 32. As shown in FIG. 5, the CESL 32 disposed in between two adjacent gate electrodes 14 are merged in the deposition process due to the reduced feature size. This results in the generation of seam 33 in the CESL 32.
As shown in FIG. 6, a photoresist layer (not shown) is used as an etching hard mask to etch the ILD layer 34. The etching of the ILD layer 34 stops on the CESL 32. Subsequently, the exposed CESL 32 is etched, thereby forming contact holes 46. As shown in FIGS. 7 and 8, a metal layer 47, is filled into the contact holes 46 to form the contact plug. However, the metal layer also fills into the seam 33 and thus causes the short circuit between adjacent contact plugs. This phenomenon is referred to as contact-to-contact bridge.
In light of the above problems, there is a need in this industry to provide an improved method of fabricating contact holes in which the contact sheet resistance is reduced without affecting the contact hole profile formed in the ILD layer and in which the seam issue is prevented.